Project 03 Solution

IMPORTANT!




Please follow the submission guidelines below or your submission will be rejected.




You are expected to submit both a lab report and the source files to Blackboard in a single submission attempt.
The source codes must be under a single project.



The VHDL project needs to be exported from Xilinx ISE Design Suite. To export VHDL project file, please refer to Blackboard - Content - Lab - Exporting VHDL Project Files.



Naming convention:
Report: “FirstName_LastName_Project_XX_MMY.pdf”




Project: “FirstName_LastName_Project_XX_MMY.zip”




Replace “XX” and “Y” with the actual project number and section number, respectively.










In this project, students are expected to use the Xilinx ISE Design Suite (Webpack edition) 14.7 to complete the following tasks.




Please read the instructions carefully. Failing to follow the instructions would lead to significant point deductions.




Task 1: S′-R′ Latch (10 points)




An S′-R′ latch operates according to the following function table.














































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Write a VHDL program to implement an S′-R′ latch using structural design. Please adopt the following entity declaration.








































Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.




















































Requirements:




In your VHDL implementation please follow the structural design method.




Deliverables:



































































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Your report:




Use your own language to describe the function of the module to be implemented in VHDL. (1 point)



Draw a circuit diagram of the module to show the design. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each test case with screenshots. Show why the simulation result is correct. (3 points)



Your project file(s):

Can compile without any errors. (2 point)
Can run simulations without any errors. (2 point)



Note: no points will be given if requirements are not satisfied.













Task 2: S-R Latch with enable (10 points)




An S-R latch with enable operates according to the following function table.





































It can be built based on a S′-R′ Latch. Write a VHDL program to implement the S-R Latch with Enable using structural design. Please adopt the following entity declaration.

















































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Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time.
























































































Requirement(s):




In your VHDL implementation

Please follow the structural design method;
Make use of the module(s) you implemented before.



Deliverable(s):






































































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Your report:




Use your own language to describe the function of the module to be implemented in VHDL. (1 point)



Draw a circuit diagram of the module to show the design. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (3 points)



Your project file(s):

Can compile without any errors. (2 point)
Can run simulations without any errors. (2 point)



Note: no points will be given if requirements are not satisfied.













Task 3: D-Latch (10 points)




Build a D latch in Xilinx according to the following function table.































The D latch can be built based on an S-R Latch with Enable. Write a VHDL program to implement the D latch using structural design. Please adopt the following entity declaration.























































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Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names,































signal values, and the time.




Requirement(s):

In your VHDL implementation

Please follow the structural design method;
Make use of the module(s) you implemented before.



Deliverable(s):




Your report:




Use your own language to describe the function of the module to be implemented in VHDL. (1 point)



Draw a circuit diagram of the module to show the design. (1 point)



Include your VHDL entity declaration(s), architecture definition(s) and the testbench program. (1 point)



Show simulation results (e.g. the waveforms). Explain the outcome of each testcase with screenshots. Show why the simulation result is correct. (3 point)



Your project file(s):

Can compile without any errors. (2 point)



Can run simulations without any errors. (2 point)



Note: no points will be given if requirements are not satisfied.























































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